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GLOBAL CONSTRAINT




SystemVerilog allows to have constraints between variables of different objects. These are called global constraints. Using the hierarchy notation, constraints can be applied on variables of different objects. When object is randomized, so are the contained objects and all other constraints are considered simultaneously.



EXAMPLE:
class child;
rand int Var1;
endclass

class parent;
rand child child_obj;
rand int Var2;
constraint global_c { Var2 < child_obj.Var1 ;}
function new();
child_obj = new();
endfunction
endclass

program random_37;
initial
for(int i=0;i<5;i++)
begin
parent parent_obj;
parent_obj = new ();
void'(parent_obj.randomize ());
$display(" Var1 = %0d ,Var2 = %0d ",parent_obj.child_obj.Var1,parent_obj.Var2 );
end
endprogram


RESULTS:

# Var1 = 903271284 ,Var2 = -1102515531
# Var1 = 2112727279 ,Var2 = -838916208
# Var1 = 1614679637 ,Var2 = 1572451945
# Var1 = 1284140376 ,Var2 = -373511538
# Var1 = 463675676 ,Var2 = -516850003

Index
Constrained Random Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Randomization Methods
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
External Constraints
Randomization Controlability
Static Constraint
Constraint Expression
Variable Ordering
Constraint Solver Speed
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits

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