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PHASE 7 RECEIVER




In this phase, we will write a receiver and use the receiver in environment class to collect the packets coming from the switch output_interface.


Receiver



Receiver collects the data bytes from the interface signal. And then unpacks the bytes in to packet using unpack_bytes method and pushes it into Rcvr2Sb_port for score boarding.

Receiver class is written in Reveicer.sv file.

Receiver class is defined by extending uvm_component class. It will drive the received transaction to scoreboard using uvm_analysis_port.





1) Define Receiver class by extending uvm_component.


`ifndef GUARD_RECEIVER
`define GUARD_RECEIVER

class Receiver extends uvm_component;

endclass : Receiver

`endif


2) Declare configuration class object.


Configuration cfg;


3) Declare an integer to hold the receiver number.


integer id;


4) Declare a virtual interface of dut out put side.


virtual output_interface.OP output_intf;


5) Declare analysis port which is used by receiver to send the received transaction to scoreboard.


uvm_analysis_port #(Packet) Rcvr2Sb_port;


6) Declare the utility macro. This utility macro provides the implementation of creat() and get_type_name() methods.


`uvm_component_utils(Receiver)


7) Define the constructor.


function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new


8) Define the build method and construct the Rcvr2Sb_port.


virtual function void build();
super.build();
Rcvr2Sb_port = new("Rcvr2Sb", this);
endfunction : build


9) In the end_of_elaboration() method, get the configuration object using get_config_object and update the virtual interfaces.


virtual function void end_of_elaboration();
uvm_object tmp;
super.end_of_elaboration();
assert(get_config_object("Configuration",tmp));
$cast(cfg,tmp);
output_intf = cfg.output_intf[id];
endfunction : end_of_elaboration


10) Define the run() method. This method collects the packets from the DUT output interface and unpacks it into high level transaction using transactions unpack_bytes() method.


virtual task run();
Packet pkt;
fork
forever
begin
// declare the queue and dynamic array here
// so they are automatically allocated for every packet
bit [7:0] bq[$],bytes[];

repeat(2) @(posedge output_intf.clock);
wait(output_intf.cb.ready)
output_intf.cb.read <= 1;

repeat(2) @(posedge output_intf.clock);
while (output_intf.cb.ready)
begin
bq.push_back(output_intf.cb.data_out);
@(posedge output_intf.clock);
end
bytes = new[bq.size()] (bq); // Copy queue into dyn array

output_intf.cb.read <= 0;
@(posedge output_intf.clock);
uvm_report_info(get_full_name(),"Received packet ...",UVM_LOW);
pkt = new();
void'(pkt.unpack_bytes(bytes));
Rcvr2Sb_port.write(pkt);
end
join

endtask : run



(S)Receiver class source code
`ifndef GUARD_RECEIVER
`define GUARD_RECEIVER

class Receiver extends uvm_component;

virtual output_interface.OP output_intf;

Configuration cfg;

integer id;

uvm_analysis_port #(Packet) Rcvr2Sb_port;

`uvm_component_utils(Receiver)

function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new


virtual function void build();
super.build();
Rcvr2Sb_port = new("Rcvr2Sb", this);
endfunction : build

virtual function void end_of_elaboration();
uvm_object tmp;
super.end_of_elaboration();
assert(get_config_object("Configuration",tmp));
$cast(cfg,tmp);
output_intf = cfg.output_intf[id];
endfunction : end_of_elaboration

virtual task run();
Packet pkt;
fork
forever
begin
// declare the queue and dynamic array here
// so they are automatically allocated for every packet
bit [7:0] bq[$],bytes[];

repeat(2) @(posedge output_intf.clock);
wait(output_intf.cb.ready)
output_intf.cb.read <= 1;

repeat(2) @(posedge output_intf.clock);
while (output_intf.cb.ready)
begin
bq.push_back(output_intf.cb.data_out);
@(posedge output_intf.clock);
end
bytes = new[bq.size()] (bq); // Copy queue into dyn array

output_intf.cb.read <= 0;
@(posedge output_intf.clock);
uvm_report_info(get_full_name(),"Received packet ...",UVM_LOW);
pkt = new();
void'(pkt.unpack_bytes(bytes));
Rcvr2Sb_port.write(pkt);
end
join

endtask : run

endclass : Receiver

Environment Class Updates



We will update the Environment class and take instance of receiver and run the testcase.





1) Declare 4 receivers.


Receiver Rcvr[4];


2) In the build() method construct the Receivers using create() methods. Also update the id variable of the receiver object.


foreach(Rcvr[i]) begin
Rcvr[i] = Receiver::type_id::create($psprintf("Rcvr%0d",i),this);
Rcvr[i].id = i;
end

(S) Environment class source code

`ifndef GUARD_ENV
`define GUARD_ENV

class Environment extends uvm_env;

`uvm_component_utils(Environment)

Sequencer Seqncr;
Driver Drvr;

Receiver Rcvr[4];

function new(string name , uvm_component parent = null);
super.new(name, parent);
endfunction: new

virtual function void build();
super.build();
uvm_report_info(get_full_name(),"START of build ",UVM_LOW);
Drvr = Driver::type_id::create("Drvr",this);
Seqncr = Sequencer::type_id::create("Seqncr",this);

foreach(Rcvr[i]) begin
Rcvr[i] = Receiver::type_id::create($psprintf("Rcvr%0d",i),this);
Rcvr[i].id = i;
end

uvm_report_info(get_full_name(),"END of build ",UVM_LOW);
endfunction

virtual function void connect();
super.connect();
uvm_report_info(get_full_name(),"START of connect ",UVM_LOW);
Drvr.seq_item_port.connect(Seqncr.seq_item_export);
uvm_report_info(get_full_name(),"END of connect ",UVM_LOW);
endfunction

endclass : Environment
`endif

(S)Download the Source Code


uvm_switch_7.tar
Browse the code in uvm_switch_7.tar


(S)Command to run the simulation


VCS Users : make vcs
Questa Users: make questa



(S)Log report after simulation

UVM_INFO @ 0 [RNTST] Running test test1...
UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] START of build
UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] END of build
UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] START of connect
UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] END of connect
----------------------------------------------------------------------
Name Type Size Value
----------------------------------------------------------------------
Seqncr Sequencer - Seqncr@14
--rsp_export uvm_analysis_export - rsp_export@16
--seq_item_export uvm_seq_item_pull_+ - seq_item_export@40
--default_sequence string 19 uvm_random_sequence
--count integral 32 -1
--max_random_count integral 32 'd10
--sequences array 5 -
----[0] string 19 uvm_random_sequence
----[1] string 23 uvm_exhaustive_sequ+
----[2] string 19 uvm_simple_sequence
----[3] string 23 Seq_device0_and_dev+
----[4] string 19 Seq_constant_length
--max_random_depth integral 32 'd4
--num_last_reqs integral 32 'd1
--num_last_rsps integral 32 'd1
----------------------------------------------------------------------
UVM_INFO @ 30: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Start of reset_dut() method
UVM_INFO @ 70: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
End of reset_dut() method
UVM_INFO @ 70: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Start of cfg_dut() method
UVM_INFO @ 110: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Port 0 Address 00
UVM_INFO @ 130: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Port 1 Address 01
UVM_INFO @ 150: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Port 2 Address 02
UVM_INFO @ 170: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Port 3 Address 03
UVM_INFO @ 190: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
End of cfg_dut() method
UVM_INFO @ 210: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Driving packet ...
UVM_INFO @ 590: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Driving packet ...
UVM_INFO @ 610: uvm_test_top.t_env.Rcvr0 [uvm_test_top.t_env.Rcvr0]
Received packet ...
UVM_INFO @ 970: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Driving packet ...
UVM_INFO @ 990: uvm_test_top.t_env.Rcvr0 [uvm_test_top.t_env.Rcvr0]
Received packet ...

--- UVM Report Summary ---

** Report counts by severity
UVM_INFO : 18
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0

Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Configuration
Phase 3 Environment N Testcase
Phase 4 Packet
Phase 5 Sequencer N Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard

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