In this phase we will implement the configuration class. All the requirements of the testbench configurations will be declared inside this class. Virtual interfaces required by verification components driver and receiver for connecting to DUT are declared in this class. We will also declare 4 variables which will hold the port address of the DUT.
uvm_object does not have the simulation phases and can be used in get_config_object and set_config_object method. So we will implement the configuration class by extending uvm_object.
1) Define configuration class by extending uvm_object
In top module we will create an object of the above defined configuration class and update the interfaces so that all the verification components can access to physical interfaces in top module using configuration class object.
1) Declare a Configuration class object
2) Construct the configuration object and update the interfaces.