This Document describes the Verification Plan for Switch. The Verification Plan is based on System Verilog Hardware Verification Language. The methodology used for Verification is Constraint random coverage driven verification.
This section contains list of all the features to be verified.
Description: Configure all the 4 port address with unique values.
ID: Packet DA
Description: DA field of packet should be any of the port address. All the 4 port address should be used.
ID : Packet payload
Description: Length can be from 0 to 255. Send packets with all the lengths.
Length field contains length of the payload.
Send Packet with correct length field and incorrect length fields.
Good FCS: Send packet with good FCS.
Bad FCS: Send packet with corrupted FCS.
Stimulus Generation Plan
1) Packet DA: Generate packet DA with the configured address.
2) Payload length: generate payload length ranging from 2 to 255.
3) Correct or Incorrect Length field.
4) Generate good and bad FCS.
1) Cover all the port address configurations.
2) Cover all the packet lengths.
3) Cover all correct and incorrect length fields.
4) Cover good and bad FCS.
5) Cover all the above combinations.