1) We will write SystemVerilog Interfaces for input port, output port and memory port.
2) We will write Top module where testcase and DUT instances are done.
3) DUT and TestBench interfaces are connected in top module.
4) Clock is generator in top module.
NOTE: In every file you will see the syntax
`ifndef GUARD_*
`endif GUARD_*
Interfaces
In the interface.sv file, declare the 3 interfaces in the following way.
All the interfaces has clock as input.
All the signals in interface are logic type.
All the signals are synchronized to clock except reset in clocking block.
Signal directional w.r.t TestBench is specified with modport.
`ifndef GUARD_INTERFACE
`define GUARD_INTERFACE
//////////////////////////////////////////
// Interface declaration for the memory///
//////////////////////////////////////////
////////////////////////////////////////////
// Interface for the input side of switch.//
// Reset signal is also passed hear. //
////////////////////////////////////////////
interface input_interface(inputbit clock);
logic data_status;
logic [7:0] data_in;
logic reset;
/////////////////////////////////////////////////
// Interface for the output side of the switch.//
// output_interface is for only one output port//
/////////////////////////////////////////////////
Testcase is a program block which provides an entry point for the test and creates a scope that encapsulates program-wide data. Currently this is an empty testcase which just ends the simulation after 100 time units. Program block contains all the above declared interfaces as arguments. This testcase has initial and final blocks.
`ifndef GUARD_TESTCASE
`define GUARD_TESTCASE
program testcase(mem_interface.MEM mem_intf,input_interface.IP input_intf,output_interface.OP output_intf[4]);
initial begin $display(" ******************* Start of testcase ****************");
#1000;
end
final $display(" ******************** End of testcase *****************");
endprogram `endif
Top Module
The modules that are included in the source text but are not instantiated are called top modules. This module is the highest scope of modules. Generally this module is named as "top" and referenced as "top module". Module name can be anything.
Do the following in the top module:
1)Generate the clock signal.
bit Clock;
initial forever #10 Clock = ~Clock;
2)Do the instances of memory interface.
mem_interface mem_intf(Clock);
3)Do the instances of input interface.
input_interface input_intf(Clock);
4)There are 4 output ports. So do 4 instances of output_interface.
output_interface output_intf[4](Clock);
5)Do the instance of testcase and pass all the above declared interfaces.
testcase TC (mem_intf,input_intf,output_intf);
6)Do the instance of DUT.
switch DUT (.
7)Connect all the interfaces and DUT. The design which we have taken is in verilog. So Verilog DUT instance is connected signal by signal.
/////////////////////////////////////////////////////
// Clock Declaration and Generation //
/////////////////////////////////////////////////////
bit Clock;