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INTERFACE
Define vera shell interface. For the reciver component, use ports. Defing a port and connect four binds.
CODE:interface.vr
interface intf {
input clk CLOCK ;
output data_status PHOLD #1 ;
output[7:0] data_in PHOLD #1 ;
input [7:0] data_out_0 PSAMPLE #-1 ;
input [7:0] data_out_1 PSAMPLE #-1 ;
input [7:0] data_out_2 PSAMPLE #-1 ;
input [7:0] data_out_3 PSAMPLE #-1 ;
input ready_0 PSAMPLE #-1 ;
input ready_1 PSAMPLE #-1 ;
input ready_2 PSAMPLE #-1 ;
input ready_3 PSAMPLE #-1 ;
output read_0 PHOLD #1 ;
output read_1 PHOLD #1 ;
output read_2 PHOLD #1 ;
output read_3 PHOLD #1 ;
output [7:0] mem_data PHOLD #1 ;
output [1:0] mem_add PHOLD #1 ;
output reset PHOLD #1 ;
output mem_en PHOLD #1 ;
output mem_rd_wr PHOLD #1 ;
}
port rec_ports {
data_out;
ready;
read;
}
bind rec_ports rec_0 {
data_out intf.data_out_0;
ready intf.ready_0;
read intf.read_0;
}
bind rec_ports rec_1 {
data_out intf.data_out_1;
ready intf.ready_1;
read intf.read_1;
}
bind rec_ports rec_2 {
data_out intf.data_out_2;
ready intf.ready_2;
read intf.read_2;
}
bind rec_ports rec_3 {
data_out intf.data_out_3;
ready intf.ready_3;
read intf.read_3;
}
Define vera shell interface. For the reciver component, use ports. Defing a port and connect four binds.
CODE:interface.vr
interface intf {
input clk CLOCK ;
output data_status PHOLD #1 ;
output[7:0] data_in PHOLD #1 ;
input [7:0] data_out_0 PSAMPLE #-1 ;
input [7:0] data_out_1 PSAMPLE #-1 ;
input [7:0] data_out_2 PSAMPLE #-1 ;
input [7:0] data_out_3 PSAMPLE #-1 ;
input ready_0 PSAMPLE #-1 ;
input ready_1 PSAMPLE #-1 ;
input ready_2 PSAMPLE #-1 ;
input ready_3 PSAMPLE #-1 ;
output read_0 PHOLD #1 ;
output read_1 PHOLD #1 ;
output read_2 PHOLD #1 ;
output read_3 PHOLD #1 ;
output [7:0] mem_data PHOLD #1 ;
output [1:0] mem_add PHOLD #1 ;
output reset PHOLD #1 ;
output mem_en PHOLD #1 ;
output mem_rd_wr PHOLD #1 ;
}
port rec_ports {
data_out;
ready;
read;
}
bind rec_ports rec_0 {
data_out intf.data_out_0;
ready intf.ready_0;
read intf.read_0;
}
bind rec_ports rec_1 {
data_out intf.data_out_1;
ready intf.ready_1;
read intf.read_1;
}
bind rec_ports rec_2 {
data_out intf.data_out_2;
ready intf.ready_2;
read intf.read_2;
}
bind rec_ports rec_3 {
data_out intf.data_out_3;
ready intf.ready_3;
read intf.read_3;
}
Index
Dut Specification
Rtl
Top
Interface
Packet
Packet Generator
Cfg Driver
Driver
Reciever
Scoreboard
Env
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Dut Specification
Rtl
Top
Interface
Packet
Packet Generator
Cfg Driver
Driver
Reciever
Scoreboard
Env
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!