This is simple verification environment.
It has, packet, Packet generator, Driver, Scoreboard, Receiver, Coverage and Config driver components.
Top module contains the instance of the Dut and verification environment.
It also has the clock generator. For more information about clock generation, go through TB_CONCEPTS in this website.
Creat an Interface and make an instance of the interface file.
Connect the interface instance to dut.
Creat an instance of the program block. Program block containg all the verification component.
CODE: top module top();
//Declare clock signal
//Signals for Assertion and to view the class proprties in Waveform viewer
wire [7:0] data_in;
wire [3:0][7:0] data_out;
wire [3:0] ready;
wire [3:0] read;
wire [7:0] mem_data;
wire [1:0] mem_add;