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AND GATE EVC


CODE : item.e
<'
type vector_kind: [INPUT, OUTPUT];

struct vector_s like any_sequence_item{
kind : vector_kind;
a: bit;
b: bit;
output : bit;
};
'>

CODE : sequence.e
<'

sequence vector_sequence using item = vector_s,
created_driver = seq_driver,
created_kind = seq_kind_t;


extend vector_sequence {
!vector : vector_s;
};

'>

CODE : main_seq.e
<'
extend MAIN vector_sequence {

// Limit the no. of sequences (use predefined count)
keep soft count == 10;

// Start start assertion ...
pre_body() @sys.any is first {
driver.raise_objection(TEST_DONE);
};

// Call's stop_run after end of all sequences (refer erm)
post_body() @sys.any is also {
wait [20] * cycle @driver.clock;
driver.drop_objection(TEST_DONE);
};
};

'>

CODE : seq_driver_h.e
<'
extend seq_driver {
agent : agent_u;
};
'>

CODE : seq_driver.e
<'

extend seq_driver {
event clock is only @agent.clk;
keep bfm_interaction_mode == PULL_MODE;

send_items() @clock is {
var item: vector_s;
while TRUE {
item = get_next_item();
agent.bfm.send_vector(item);
emit item_done;
};
};

run() is also {
start send_items();
};
};

'>

CODE : testcase.e
<'
extend MAIN vector_sequence {

body()@driver.clock is only{
//for i from 0 to 9 {
do vector keeping {
.kind == INPUT;
};
print vector.a;
print vector.b;
do vector keeping {
.kind == OUTPUT;
};
print vector.output;
//};

};
};
'>

CODE : agent_h.e
<'
unit agent_u {
};
'>
CODE : agent.e
<'
extend agent_u {

keep hdl_path() == "~/and_gate_tb";

bfm: bfm_u is instance;
driver : seq_driver is instance;
coverage : coverage_u is instance;
sb: scoreboard_u is instance;
monitor: monitor_u is instance;

sig_a :string;
sig_b :string;
sig_c :string;
sig_clk:string;

verilog task '$shm_close'();

verilog variable 'a' using wire;
verilog variable 'b' using wire;
verilog variable 'c' using wire;

keep bfm.agent == me;
keep driver.agent == me;
keep coverage.agent == me;
keep monitor.agent == me;

keep sig_a =="a";
keep sig_b == "b";
keep sig_c == "c";
keep sig_clk == "clk";
event clk is rise('(sig_clk)')@sim;

close_waveform() @clk is {
'$shm_close'();
wait [2]* cycle;
sys.drop_objection(TEST_DONE);
};

};
'>

CODE : coverage_h.e
<'
unit coverage_u {
agent:agent_u;
event cover_event;
};
'>
~
CODE : coverage.e
<'
extend coverage_u {

cover cover_event using text="coverage for inputs a,b" is {
item a : bit = agent.sb.a;
item b : bit = agent.sb.b;
cross a,b using text="cross coverage";
};
};

'>
CODE : scoreboard_h.e
<'
unit scoreboard_u {
};
'>

CODE : scoreboard.e
'
extend scoreboard_u {
a:bit;
b:bit;
output:bit;
};

'>

CODE : monitor_h.e
<'
unit monitor_u {
agent: agent_u;
};
'>
CODE : monitor.e
<'
extend monitor_u {

checker() is{

if ((agent.sb.a & agent.sb.b) == agent.sb.output) {
}
else {
dut_error("output mismatch");
};
};
};

'>


CODE : bfm_h.e
<'

unit bfm_u {
agent: agent_u;

};

'>

CODE : bfm.e
<'
extend bfm_u {

event clk is @agent.clk;

send_vector(vec:vector_s)@clk is {
if vec.kind == INPUT {
'(agent.sig_a)'= vec.a;
'(agent.sig_b)'= vec.b;
wait[1];
agent.sb.a= vec.a;
agent.sb.b= vec.b;
emit agent.coverage.cover_event;
};
if vec.kind == OUTPUT {
vec.output='(agent.sig_c)';
agent.sb.output=vec.output ;
wait[1];
agent.monitor.checker();
};
};
};
'>

CODE : env.e
<'
unit env_u{
agent: agent_u is instance;

};

'>

CODE : top.e
<'
import import_files.e;

extend sys{
env : env_u is instance;

stop_wave: bool;

keep soft stop_wave == FALSE;
all_objections_dropped(kind: objection_kind) is also {
if kind == TEST_DONE and !stop_wave {
raise_objection(TEST_DONE);
start env.agent.close_waveform();
message(LOW,"close_waveform()");
stop_wave = TRUE;
};
};



};
'>









Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Temporal Expressions
Temporal Operators 1
Temporal Operators 2
Synchronizing With The Simulator
Wait And Sync
Physical Virual Feilds
Packing N Unpacking
Pre Run N On The Fly
Coverage
Commands
Extendable Methods
Non Extendable Methods
And Gate Evc

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