The OVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog.
OVM library contains:
Component classes for building testbench components like generator/driver/monitor etc.
Reporting classes for logging,
Factory for object substitution.
Synchronization classes for managing concurrent process.
Policy classes for printing, comparing, recording, packing, and unpacking of ovm_object based classes.
TLM Classes for transaction level interface.
Sequencer and Sequence classes for generating realistic stimulus.
And Macros which can be used for shorthand notation of complex implementation.
In this tutorial, we will learn some of the OVM concepts with examples.