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PHASE 2 CONFIGURATION




In this phase we will implement the configuration class. All the requirements of the testbench configurations will be declared inside this class. Virtual interfaces required by verification components driver and receiver for connecting to DUT are declared in this class. We will also declare 4 variables which will hold the port address of the DUT.

ovm_object does not have the simulation phases and can be used in get_config_object and set_config_object method. So we will implement the configuration class by extending ovm_object.



Configuration



1) Define configuration class by extending ovm_object


`ifndef GUARD_CONFIGURATION
`define GUARD_CONFIGURATION

class Configuration extends ovm_object;

endclass : Configuration

`endif


2) Declare All the interfaces which are required in this verification environment.


virtual input_interface.IP input_intf;
virtual mem_interface.MEM mem_intf;
virtual output_interface.OP output_intf[4];


3) Declare 4 variables which holds the device port address.


bit [7:0] device0_add ;
bit [7:0] device1_add ;
bit [7:0] device2_add ;
bit [7:0] device3_add ;


4) ovm_object required to define the ovm_object::creat() method.
ovm_object::create method allocates a new object of the same type as this object and returns it via a base ovm_object handle.

In create method, we have to construct a new object of configuration class and update all the important fields and return it.


virtual function ovm_object create(string name="");
Configuration t = new();

t.device0_add = this.device0_add;
t.device1_add = this.device1_add;
t.device2_add = this.device2_add;
t.device3_add = this.device3_add;
t.input_intf = this.input_intf;
t.mem_intf = this.mem_intf;
t.output_intf = this.output_intf;

return t;
endfunction : create

(S)Configuration class source code
`ifndef GUARD_CONFIGURATION
`define GUARD_CONFIGURATION

class Configuration extends ovm_object;

virtual input_interface.IP input_intf;
virtual mem_interface.MEM mem_intf;
virtual output_interface.OP output_intf[4];

bit [7:0] device0_add ;
bit [7:0] device1_add ;
bit [7:0] device2_add ;
bit [7:0] device3_add ;

virtual function ovm_object create(string name="");
Configuration t = new();

t.device0_add = this.device0_add;
t.device1_add = this.device1_add;
t.device2_add = this.device2_add;
t.device3_add = this.device3_add;
t.input_intf = this.input_intf;
t.mem_intf = this.mem_intf;
t.output_intf = this.output_intf;

return t;
endfunction : create

endclass : Configuration
`endif

Updates To Top Module



In top module we will create an object of the above defined configuration class and update the interfaces so that all the verification components can access to physical interfaces in top module using configuration class object.




1) Declare a Configuration class object


Configuration cfg;


2) Construct the configuration object and update the interfaces.


initial begin
cfg = new();
cfg.input_intf = input_intf;
cfg.mem_intf = mem_intf;
cfg.output_intf = output_intf;


3) In top module , we have to call the run_test() method.


run_test();

(S) Top module updates

typedef class Configuration;

module top();
/////////////////////////////////////////////////////
// Clock Declaration and Generation //
/////////////////////////////////////////////////////
bit Clock;

initial
begin
#20;
forever #10 Clock = ~Clock;
end
/////////////////////////////////////////////////////
// Memory interface instance //
/////////////////////////////////////////////////////
mem_interface mem_intf(Clock);
/////////////////////////////////////////////////////
// Input interface instance //
/////////////////////////////////////////////////////
input_interface input_intf(Clock);
/////////////////////////////////////////////////////
// output interface instance //
/////////////////////////////////////////////////////
output_interface output_intf[4](Clock);

/////////////////////////////////////////////////////
// Creat Configuration and Strart the run_test//
/////////////////////////////////////////////////////

Configuration cfg;

initial begin
cfg = new();
cfg.input_intf = input_intf;
cfg.mem_intf = mem_intf;
cfg.output_intf = output_intf;

run_test();
end

/////////////////////////////////////////////////////
// DUT instance and signal connection //
/////////////////////////////////////////////////////
switch DUT (.clk(Clock),
.reset(input_intf.reset),
.data_status(input_intf.data_status),
.data(input_intf.data_in),
.port0(output_intf[0].data_out),
.port1(output_intf[1].data_out),
.port2(output_intf[2].data_out),
.port3(output_intf[3].data_out),
.ready_0(output_intf[0].ready),
.ready_1(output_intf[1].ready),
.ready_2(output_intf[2].ready),
.ready_3(output_intf[3].ready),
.read_0(output_intf[0].read),
.read_1(output_intf[1].read),
.read_2(output_intf[2].read),
.read_3(output_intf[3].read),
.mem_en(mem_intf.mem_en),
.mem_rd_wr(mem_intf.mem_rd_wr),
.mem_add(mem_intf.mem_add),
.mem_data(mem_intf.mem_data));
endmodule : top
`endif

(S)Download the source code


ovm_switch_2.tar
Browse the code in ovm_switch_2.tar


(S)Command to compile


vcs -sverilog +incdir+$OVM_HOME/src $OVM_HOME/src/ovm_pkg.sv +incdir+. rtl.sv interface.sv top.sv
qverilog +incdir+$OVM_HOME/src $OVM_HOME/src/ovm_pkg.sv +incdir+. rtl.sv interface.sv top.sv


Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Configuration
Phase 3 Environment N Testcase
Phase 4 Packet
Phase 5 Sequencer N Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard

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