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OTHER OOPS FEATURES
Multiple inheritence and Function overloading and the OOPs features which are not supported by System Verilog.
Multiple Inheritence
Multiple inheritance refers to a feature of some object-oriented programming languages in which a class can inherit behaviors and features from more than one superclass. This contrasts with single inheritance, where a class may inherit from at most one superclass. SystemC supports multiple inheritance, SystemVerilog supports only single inheritance.
Multiple inheritance allows a class to take on functionality from multiple other classes, such as allowing a class named D to inherit from a class named A, a class named B, and a class named C.
EXAMPLE:
class A;
.....
endclass
class B;
......
endclass
class C;
......
endclass
class D extends A,B,C;
.....
endclass
Multiple inheritance is not implemented well in SystemVerilog languages . Implementation problems include:
Increased complexity
Not being able to explicitly inherit from multiple times from a single class
Order of inheritance changing class semantics.
Method Overloading
Method overloading is the practice of declaring the same method with different signatures. The same method name will be used with different data type . This is Not Supported by SystemVerilog as of 2008.
EXAMPLE:
task my_task(integer i) { ... }
task my_task(string s) { ... }
program test {
integer number = 10;
string name = "vera";
my_task(number);
my_task(name);
}
Multiple inheritence and Function overloading and the OOPs features which are not supported by System Verilog.
Multiple Inheritence
Multiple inheritance refers to a feature of some object-oriented programming languages in which a class can inherit behaviors and features from more than one superclass. This contrasts with single inheritance, where a class may inherit from at most one superclass. SystemC supports multiple inheritance, SystemVerilog supports only single inheritance.
Multiple inheritance allows a class to take on functionality from multiple other classes, such as allowing a class named D to inherit from a class named A, a class named B, and a class named C.
EXAMPLE:
class A;
.....
endclass
class B;
......
endclass
class C;
......
endclass
class D extends A,B,C;
.....
endclass
Multiple inheritance is not implemented well in SystemVerilog languages . Implementation problems include:
Increased complexity
Not being able to explicitly inherit from multiple times from a single class
Order of inheritance changing class semantics.
Method Overloading
Method overloading is the practice of declaring the same method with different signatures. The same method name will be used with different data type . This is Not Supported by SystemVerilog as of 2008.
EXAMPLE:
task my_task(integer i) { ... }
task my_task(string s) { ... }
program test {
integer number = 10;
string name = "vera";
my_task(number);
my_task(name);
}
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution Operator
Null
External Declaration
Classes And Structures
Typedef Class
Pure
Other Oops Features
Misc
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution Operator
Null
External Declaration
Classes And Structures
Typedef Class
Pure
Other Oops Features
Misc
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!