Multiple inheritence and Function overloading and the OOPs features which are not supported by System Verilog.
Multiple inheritance refers to a feature of some object-oriented programming languages in which a class can inherit behaviors and features from more than one superclass. This contrasts with single inheritance, where a class may inherit from at most one superclass. SystemC supports multiple inheritance, SystemVerilog supports only single inheritance.
Multiple inheritance allows a class to take on functionality from multiple other classes, such as allowing a class named D to inherit from a class named A, a class named B, and a class named C.
EXAMPLE: class A;
class D extends A,B,C;
Multiple inheritance is not implemented well in SystemVerilog languages . Implementation problems include:
Not being able to explicitly inherit from multiple times from a single class
Order of inheritance changing class semantics.
Method overloading is the practice of declaring the same method with different signatures. The same method name will be used with different data type . This is Not Supported by SystemVerilog as of 2008.