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///////////////////////////////////////
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//// ////
//// VMM 1.2 example ////
//// ////
//// For more vmm examples ////
//// visit www.testbench.in ////
//// ////
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//-----------------------------------------------------------------------------
// Generic dummy trl Interface
//-----------------------------------------------------------------------------
`define WIDTH 8
interface dut_if (input logic clk);
logic [`WIDTH-1:0] address;
logic [`WIDTH-1:0] i_data;
logic [`WIDTH-1:0] o_data;
logic rdwr;
logic en;
logic reset;
clocking drv @ (posedge clk);
default input #1ps output #1ps;
output reset, en, rdwr, address, o_data;
endclocking : drv
clocking mon @ (posedge clk);
default input #1ps output #1ps;
input reset, en, rdwr, address, i_data, o_data;
endclocking : mon
modport driver (import drv.*, input clk);
modport monitor (import mon.*, input clk);
endinterface : dut_if
//-----------------------------------------------------------------------------
// end of file
//-----------------------------------------------------------------------------