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| /////////////////////////////////////// /////////////////////////////////////// //// //// //// VMM 1.2 example //// //// //// //// For more vmm examples //// //// visit www.testbench.in //// //// //// /////////////////////////////////////// /////////////////////////////////////// //----------------------------------------------------------------------------- // environment top module //----------------------------------------------------------------------------- `include "dummy_rtl.v" `include "vmm_interface.sv" module top; `include "vmm_cfg.sv" `include "vmm_packet.sv" `include "vmm_gen.sv" `include "vmm_drv.sv" `include "vmm_cov.sv" `include "vmm_rcv.sv" `include "vmm_sbd.sv" `include "vmm_scn.sv" `include "vmm_env.sv" // clock generation reg clk; initial begin clk = 1'b0; forever #5 clk = ~clk; end // interface handle dut_if dut_ifc (clk); // rtl instance and port map dummy_rtl u_dut ( .address(dut_ifc.address), .i_data (dut_ifc.o_data ), .o_data (dut_ifc.i_data ), .rdwr (dut_ifc.rdwr ), .clock (dut_ifc.clk ), .en (dut_ifc.en ), .reset (dut_ifc.reset ) ); my_env env; initial begin // env constructor env = new(dut_ifc.driver, dut_ifc.monitor); env.run(); $finish; end endmodule : top //----------------------------------------------------------------------------- // end of file //----------------------------------------------------------------------------- |