../verilog/altera_mf.v ../../rtl/verilog/header.v ../../rtl/verilog/TECH/CLK_SWITCH.v ../../rtl/verilog/TECH/CLK_DIV2.v ../../rtl/verilog/TECH/duram.v ../../rtl/verilog/MAC_tx/MAC_tx_FF.v ../../rtl/verilog/MAC_tx/Ramdon_gen.v ../../rtl/verilog/MAC_tx/CRC_gen.v  ../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v ../../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v ../../rtl/verilog/MAC_tx/flow_ctrl.v ../../rtl/verilog/MAC_rx/CRC_chk.v ../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v ../../rtl/verilog/MAC_rx/MAC_rx_FF.v ../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v ../../rtl/verilog/MAC_rx/Broadcast_filter.v ../../rtl/verilog/miim/eth_clockgen.v ../../rtl/verilog/miim/eth_outputcontrol.v ../../rtl/verilog/miim/eth_shiftreg.v ../../rtl/verilog/RMON/RMON_addr_gen.v ../../rtl/verilog/RMON/RMON_ctrl.v ../../rtl/verilog/RMON/RMON_dpram.v ../../rtl/verilog/RMON.v ../../rtl/verilog/MAC_rx.v ../../rtl/verilog/MAC_tx.v ../../rtl/verilog/eth_miim.v ../../rtl/verilog/MAC_top.v ../../rtl/verilog/Phy_int.v ../../rtl/verilog/Clk_ctrl.v  ../../rtl/verilog/reg_int.v pkt.vr rx_pkt.vr chan.vr host_intf.vr host_driver.vr cfg_intf.vr host_xtor.vr host_xtor_rx.vr cfg_xtor.vr phy_intf.vr phy_driver.vr phy_xtor.vr phy_xtor_rx.vr cov.vr sb.vr call_back.vr env.vr pro.vr top.v