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| //////////////////////////////////////////////// ////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s//// ////s www.testbench.in s//// ////s s//// ////s SystemVerilog Tutorial s//// ////s s//// ////s gopi@testbench.in s//// ////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s//// //////////////////////////////////////////////// module assertion_cov(intf_cnt intf); Feature_3 : cover property (@(posedge intf.clk) (intf.count !=0) |-> intf.reset == 0 ); endmodule |