In this tutorial, we will verify the Switch RTL core using UVM in SystemVerilog. Following are the steps we follow to verify the Switch RTL core.
1) Understand the specification
2) Developing Verification Plan
3) Building the Verification Environment. We will build the Environment in Multiple phases, so it will be easy for you to lean step by step.
In this verification environment, I will not use agents and monitors to make this tutorial simple and easy.
Phase 1) We will develop the interfaces, and connect it to DUT in top module.
Phase 2) We will develop the Configuration class.
Phase 3) We will develop the Environment class and Simple testcase and simulate them.
Phase 4) We will develop packet class based on the stimulus plan. We will also write a small code to test the packet class implementation.
Phase 5) We will develop sequencer and a sample sequences.
Phase 6) We will develop driver and connect it to the Sequencer in to environment.
Phase 7) We will develop receiver and instantiate in environment.
Phase 8) We will develop scoreboard which does the comparison of the expected packet with the actual packet received from the DUT and connect it to driver and receiver in Environment class.
Installing Uvm Library
1)Go to http://www.accellera.org/activities/vip/ 2)Download the uvm*.tar.gz file.
3)Untar the file.
4)Go to the extracted directory : cd uvm*\uvm\src
5)Set the UVM_HOME path : setenv UVM_HOME `pwd`
(This is required to run the examples which are downloaded from this site)
6)Go to examples : cd ../examples/hello_world/uvm/
7)Compile the example using :
your_tool_compilation_command -f compile_<toolname>.f
(example for questasim use : qverilog -f compile_questa.f)
8)Run the example.