The attached example contains VMM 1.2 based layered testbench architeracture.
My intensation here is to demonstrate different component of testbench using
different base class of VMM.
This testbench contains a dummy rtl which is just a memory and the verification environment explorers the use of vmm_data, vmm_xactor, vmm_env, vmm_sb_ds, callback, interface, clocking block,
interface, modport,constraint randomization, covergroup, configuration etc.
Main intensation of the testbench is to demonstrate the vmm_sb_ds, which is the
scoreboard class of vmm. There are 2 streams are defined in scoreboard for
comparetion, one for driver another for monitor side. Stream is nothing but sequence
of packet. In this example, 12 packet are driven to the DUT and received from monitor,
All 12 are matched by the scoreboard.