| |||
|---|---|---|---|
|
|
||
- SystemVerilog
- Verification
- Constructs
- Interface
- OOPS
- Randomization
- Functional Coverage
- Assertion
- DPI
- UVM Tutorial
- VMM Tutorial
- OVM Tutorial
- Easy Labs : SV
- Easy Labs : UVM
- Easy Labs : OVM
- Easy Labs : VMM
- AVM Switch TB
- VMM Ethernet sample
- Verilog
- Verification
- Verilog Switch TB
- Basic Constructs
- OpenVera
- Constructs
- Switch TB
- RVM Switch TB
- RVM Ethernet sample
- Specman E
- Interview Questions
VMM 1.2 example and VMM vmm_sb_ds example
The attached example contains VMM 1.2 based layered testbench architeracture. My intensation here is to demonstrate different component of testbench using different base class of VMM.
This testbench contains a dummy rtl which is just a memory and the verification environment explorers the use of vmm_data, vmm_xactor, vmm_env, vmm_sb_ds, callback, interface, clocking block, interface, modport,constraint randomization, covergroup, configuration etc.
Main intensation of the testbench is to demonstrate the vmm_sb_ds, which is the scoreboard class of vmm. There are 2 streams are defined in scoreboard for comparetion, one for driver another for monitor side. Stream is nothing but sequence of packet. In this example, 12 packet are driven to the DUT and received from monitor, All 12 are matched by the scoreboard.
Download vmm1.2_example.tar
Browse the code in vmm1.2_example.tar
Topology of Example:
Your feedback/input/thought are welcomed which can help me to update. Reach me at mail2ajshah@gmail.com
About the author:
Ankit Shah
is working at Sibridge Technologies Pvt. Ltd, Ahmedabad,India.
Your feedback / input / thought on this article, send to Ankit @ mail2ajshah@gmail.com
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!