VCSMX Separate compilation example

When I started to use VCSMX along with system Verilog, one main problem came up: I had to generate one executable for each program.
Coming up with VCSMX version 2008.12, the separate compile feature was introduced to solve the problem; anyway the working model is quite strict. I used as a starting point "switch" example from www.testbench.in to illustrate the separate compile flow. The idea is to generate a partition of your program file that would be loaded when you launch your executable. A single image of your design is needed; if you change your program file, you would only need to analyze it and generate a new partition. Please have a look to the Makefile provided along with the testcase. The version 2008.12-2 of VCSMX was used to set up the testcase.

1. Compile your DUT

2. Compile the testbench components for a given package.

- Analyze the code with vlogan..
- Generate shared object libraries for each package with VCS.
- Repeat these steps for each package.

In VMM methodology, a class should be defined within a package, Driver.sv, packet.sv and environment.sv are now system verilog packages.
Partition should also be generated for packages [separate compile feature steps]

3. Compile the testcases.

- Analyze the code with vlogan and specify a unique partition name for each testcase.
- Generate shared object libraries for different program partitions with VCS.

4. Generate a program shell file from the program block.

This shell file is used for compiling the main simv in order to provide a hook for dynamic linking of the testbench at runtime. The testcases must have the same program block name so that only one shell file is required to load the testcases.

5. Analyze the top level testbench file:

You must compile in different libraries the test bench files and the design part. rtl.sv ' current Driver.sv, packet.sv, environment.sv and interface.sv ' testcase Top.sv interface.sv ' current Interface.sv is analyzed twice but in current and testcases libraries. This is due to the separate compile feature and also because environment.sv and top.sv instantiates interfaces.

6. Generate simv, which includes the DUT, program shell file, and top module to link the DUT with the program shell file.

7. Run simulations using the generated simv, specifying the partitions that need to be loaded

Repeat steps 3 or 4 followed by step 7 to further develop the testbench or testcases, and later in the testing cycle, to run your tests and regressions.

Download the example

About the author:

Emmanuelle Chu
is EDA support engineer at Texas Instruments (Nice Area, France). She is with TI from 2004. Emmanuelle Chu is an master in Electronics and computers from ENSSAT.

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