In 2005 there were separate standards for Verilog and SystemVerilog which are merged here with SystemVerilog 2009. There are 30+ noticeable new constructs and 25+ system task are introduced in SystemVerilog 2009.
I listed out following new constructs which are added in SV-2009.
timeunit and timeprecision
You can specify timeunit and timeprecision inside the module with single keyword.
module E (...); timeunit 100ps / 10fs; // timeunit with optional second argument
(Ch. 22.214.171.124 of LRM)
checker - endchecker
The checker is specifically created to encapsulate assertions. It can be added with the modeling code and can be instantiationed. Formal arguments of checker are inputs.
Global clocking block is declared as the global clocking block for an entire elaborated SystemVerilog model.
global clocking @(clk1 or clk2); endclocking
%p - displays as an assignment format.
%x - displays in hexadecimal format.
It is equivalent to posedge+negedge
This local score compiler directive replaces the other test macro like `define. A let construct may be instantiated in other expressions.
let declarations can be used for customization and can replace the text macros in many cases.
let check_grant(a, b) = assert( a ##2 b) );
check_grant(req, gnt); (Ch. 11.13)
Packet chaining, automatic package and multiple package export is also introduced in SV-2009.
pure virtual methods
SV-2009 allows to declare pure virtual methods as well as class. It must be written in abstract class & it must be only a prototype, It must not contain any statement and must with without endtask/endfunction.
Using fork/join_none, now time consuming constructs can be used inside function.
functionvoid disp; fork
#0 $display("%t: This is #0", $time);
#1 $display("%t: This is #1", $time);
#3 $display("%t: This is #3 and A = %x", $time, a);
a <= 8'hbb; // It allows non-blocking assignment
#2 $display("%t: This is #2", $time); join_none endfunction (Ch. 9.3.2)
covergroup with sample arguments covergroupwithfunction sample(bit a, int x); coverpoint x; cross x, a; endgroup :
These sequence operators are introduced to simulate assertion efficiently. Assert may produce wrong message if there is a glitch in the signal. strong require that some terminating condition happen in the future, and this includes the requirement that the property clock ticks enough time to enable the condition to happen. weak do not impose any requirement on the terminating condition, and do not require the clock to tick. If the strong or weak operator is omitted, then the evaluation of the sequence_expr depends on the assertion statement in which it is used. If the assertion statement is assert property or assume property, then the sequence_expr is evaluated as weak(sequence_expr). Otherwise, the sequence_expr is evaluated as strong(sequence_expr).
The default in SV-2005 was strong while in SV-2009 is weak unless you. specified
Implies and iff properties
A property is an implies if it has the following form:
property_expr1 implies property_expr2
Above form evaluates to true if property_expr1 evaluates to true, if not then
property_expr2 evaluates to true.
A property is an iff if it has the following form:
property_expr1 iff property_expr2
A property of this form evaluates to true if, and only if, either both
property_expr1 evaluates to false and property_expr2 evaluates to false or both
property_expr1 evaluates to true and property_expr2 evaluates to true.
Property s1 says that done shall be asserted at some clock tick during the first 6 clock ticks, and starting from one of the clock ticks when done is asserted, rst shall always be low. Property s2 says that done shall be asserted at some clock tick during the first 6 clock ticks, and starting the clock tick after one of the clock ticks when done is asserted, rst shall always be low.
The property operators
s_nexttime, s_always, s_eventually, s_until, s_until_with, and sequence operator strong are strong.
The property operators nexttime, always, until, eventually, until_with, and sequence operator
weak are weak.
nexttime and s_nexttime
// if the clock ticks once more, then a shall be true at the next clock tick property s1;
nexttime a; endproperty
// the clock shall tick once more and a shall be true at the next clock tick. property s2;
s_nexttime a; endproperty (Ch. 16.13)
always - s_always
a ##1 b |=> always c; endproperty
property s1 evaluates to true provided that if a is true at the first clock tick and b is true at the second clock tick, then c shall be true at every clock tick that follows the second.
until - until_with - s_until - s_until_with
a until b; endproperty
a until_with b; endproperty
Property s1 evaluates to true if, and only if, a is true at every clock tick beginning with the starting clock tick of the evaluation attempt and continuing
until, but not necessarily including, a clock tick at which b is true.
The property p3 evaluates to true provided that a is true at every clock tick beginning with the starting clock tick of the evaluation attempt and continuing
until and including a clock tick at which b is true.
eventually - s_eventually property s1;
s_eventually a; endproperty
The property s1 evaluates to true if, and only if, there exists a current or future clock tick at which a is true.
It is used to specify reserved keywords, it will give an error if implementain does not matched with version_specifier. e.g if you have specified "1800-2009" then all the previous versions of Verilog/SystemVerilog keywords can be used but if you have specified "1800-2005" then those keywords which are introduced specifically in SV-2009 those can not be used.
FILE name and LINE numbers
It keeps track of the filenames of SystemVerilog source files and line nunbers in the files. which can be helpfull to source error messages and the file name. `__FILE__ expands to the name of the current input file, in the form of a string literal constant. This is the path by which the compiler opened the file, not the short name specified in `include or as the command line argument. `__LINE__ expands to the current input line number, in the form of a decimal
$display("Internal error: null handle at %s, line %d.",`__FILE__, `__LINE__);
file path and line number will be return which contain above message.
(Ch. 22.12, 22.13)
$syatem - allows operation system commands.
$global_clock returns the event statement which is written global clocking block declaration. Here it will return "clk1 or clk2".
$sformatf - this system function returns the message into string. Thus string can be passed into valid function.
$fatel - $error - $warning - $info can be used outside assertion.
$assertpasson - enable execution of pass statement.
$assertpassoff - stop execution of pass statement.
$assertfailon - enable execution of pass statement.
$assertfailoff - stop execution of fail statement.
$assertnonvacuouson - enable execution of pass statement when assertion is vacuous.
$assertvacuousoff - stop execution of pass statement when assertion is non vacuous.
(Ch 20.14, 16.15.8)
It detect changes in values between two adjscent clock tics.