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REG AND LOGIC




Historically, Verilog used the terms wire and reg as a descriptive way to declare wires and registers. The original intent was soon lost in synthesis and verification coding styles, which soon gave way to using terns Nets and Variables in Verilog-2001. The keyword reg remained in SystemVerilog, but was now misleading its intent. SystemVerilog adds the keyword logic as a more descriptive term to remind users that it is not a hardware register. logic and reg are equivalent types.

SystemVerilog extended the variable type so that, it can be used to connect gates and modules. All variables can be written either by one continuous assignment, or by one or more procedural statements. It shall be an error to have multiple continuous assignments or a mixture of procedural and continuous assignments.

Now we saw logic and wire are closer. Wire (net) is used when driven by multiple drivers, where as logic is used when it is driven by only one driver. logic just holds the last value assigned to it, while a wire resolves its value based on all the drivers.

For example:


logic abc;



The following statements are legal assignments to logic abc:


1) assign abc = sel ? 1 : 0;
2) not (abc,pqr),
3) always #10 abc = ~abc;
Index
Introduction
Data Types
Literals
Strings
Userdefined Datatypes
Enumarations
Structures And Uniouns
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Comparison Of Arrays
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process Control

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