Verilog is loosely typed . Assignments can be done from one data type to other data types based on predefined rules.The compiler only checks that the destination variable and source expression are scalars. Otherwise, no type checking is done at compile time. Systemverilog has complex data types than Verilog. It's necessary for SystemVerilog to be much stricter about type conversions than Verilog, so Systemverilog provided the cast(`) operator, which specifies the type to use for a specific expression. Using Casting one can assign values to variables that might not ordinarily be valid because of differing data type. SystemVerilog adds 2 types of casting. Static casting and dynamic casting.
A data type can be changed by using a cast ( ' ) operation. In a static cast, the expression to be cast shall be enclosed in parentheses that are prefixed with the casting type and an apostrophe. If the expression is assignment compatible with the casting type, then the cast shall return the value that a variable of the casting type would hold after being assigned the expression.
SystemVerilog provides the $cast system task to assign values to variables that might not ordinarily be valid because of differing data type. $cast can be called as either a task or a function.
The syntax for $cast is as follows:
function int $cast( singular dest_var, singular source_exp );
task $cast( singular dest_var, singular source_exp );
The dest_var is the variable to which the assignment is made. The source_exp is the expression that is to be assigned to the destination variable. Use of $cast as either a task or a function determines how invalid assignments are handled. When called as a task, $cast attempts to assign the source expression to the destination variable. If the assignment is invalid, a run-time error occurs, and the destination variable is left unchanged.