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VIRTUAL INTERFACE


Virtual Interfaces



Virtual interfaces provide a mechanism for separating abstract models and test programs from the actual signals that make up the design. A virtual interface allows the same subprogram to operate on different portions of a design, and to dynamically control the set of signals associated with the subprogram. Instead of referring to the actual set of signals directly, users are able to manipulate a set of virtual signals.



1 module testbench(intf.tb tb_if);
2 virtual interface intf.tb local_if; // virtual interface.
3 ....
4 task read(virtual interface intf.tb l_if) // As argument to task
5 ....
6 initial
7 begin
8 Local_if = tb_if; // initializing virtual interface.
9 Local_if.cb.read <= 1; //writing to synchronous signal read
10 read(Local_if); // passing interface to task.
11 end
12 endmodule



In the above program, local_if is just like a pointer. It represents an interface instance. Using keyword "virtual" , virtual interfaces instance is created. It does not have any signal. But it can hold physical interface. Tb_if is the physical interface which is allocated during compilation time. You can drive and sample the signals in physical interface. In line 8, the physical interface tb_if is assigned to local_if. With this , we can drive and sample the physical signals. In line 9, read signal of tb_if is accessed using local_if.



Advantages Of Virtual Interface



1) Virtual interface can be used to make the TestBench independent of the physical interface. It allows developing the test component independent of the DUT port while working with multi port protocol.
2) With virtual interface, we can change references to physical interface dynamically. Without virtual interfaces, all the connectivity is determined during compilation time, and therefore can't be randomized or reconfigured.
3) In multi port environment, it allows to access the physical interfaces using array index.
4) Physical interfaces are not allowed in object oriented programming, as physical interface is allocated at compilation time itself. Virtual interface which are set at run time allows to do object oriented programming with signals rather than just with variables.
5) Virtual interface variables can be passed as arguments to tasks, functions, or methods.
6) Allows to use Equality ( == ) and inequality ( != ) .

A virtual interface must be initialized before it can be used, by default, it points to null. Attempting to use an uninitialized virtual interface will result in a run-time error.



Multi Bus Interface



If you are working on protocol which has multiple sub bus protocol, there are several ways to create interfaces.

One Big single interface with all the sub protocol signals inside it. With single interface, it is easy to pass around the whole system. You have to name all the signals with the sub protocol prefix like pcie_enable, Eth_enable etc. Restrict the access using clocking blocks else all signals can be accessed by all the modules using this interface. Reusability will be very less as all the sub protocols are in one interface.

Using multiple interfaces, one for each sub protocol, each interface for each sub bus will increase the complexity while passing around the system. No need to prefix the sub protocol name as the sub protocol name is reflected in the interface name itself. With this you can only pass the sub interfaces required by other modules. All the interfaces will be reusable as each interface represents an individual protocol.

Using one big interface with sub multiple interfaces will be easy for passing around the system. With this the sub interfaces can be reused for other components and other designs.



Index
Interface
Ports
Interface Methods
Clocking Block
Virtual Interface
Svtb N Verilog Dut

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