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PORTS


Interface Ports




In the previous example, signal clk is declared as port to the interface. Interface Ports work similar to the module ports. Members of port list can be connected externally by name or position when the interface is instantiated as shown in line 3 of module top code.



Modports



In the above example, we did not mention the direction of signals. The direction of the clk signal in input for both the Dut and Testbench modules. But for the rest of the signals, the direction is not same. To specify the direction of the signal w.r.t module which uses interface instead of port list, modports are used. Modport restrict interface access within a module based on the direction declared. Directions of signals are specified as seen from the module. In the modeport list, only signal names are used.

Let us see the modport usage with the previous example. 2 mod port definitions are needed, one for DUT and other for TestBench.

Interface declaration for the above example:


interface intf (input clk);
logic read, enable,
logic [7:0] addr,data;

modport dut (input read,enable,addr,output data);
modport tb (output read,enable,addr,input data);
endinterface :intf



In this example, the modport name selects the appropriate directional information for the interface signals accessed in the module header. Modport selection can be done in two ways. One at Module declaration , other at instantication.



Modport Selection Duing Module Definition.


module Dut (intf.dut dut_if); // declaring the interface with modport
....
assign dut_if.data = temp1 ? temp2 : temp3 ; // using the signal in interface
always @(posedge intf.clk)
....
endmodule

module Testbench(intf.tb tb_if);
.....
.....
endmodule

1 module top();
2 logic clk;
3 intf bus_if(clk); // interface instantiation
4 Dut d(bus_if); // Pass the interface
5 Testbench TB (Bus_if); // Pass the interface
6 endmodule


Modport Selection Duing Module Instance.


module Dut (intf dut_if); // declaring the interface
....
assign dut_if.data = temp1 ? temp2 : temp3 ; // using the signal in interface
always @(posedge intf.clk)
....
endmodule

module Testbench(intf tb_if);
.....
.....
endmodule

1 module top();
2 logic clk;
3 intf bus_if(clk); // interface instantiation
4 Dut d(bus_if.dut); // Pass the modport into the module
5 Testbench TB (Bus_if.tb); // Pass the modport into the module
6 endmodule



A mod port can also define expressions. They can also define their own names. Module can use the modport declared name. For example



modport dut (input read,enable,.addr(2),output .d(data[1:5]);

module dut(intf.dut dut_if);
assign dut_if.d = temp; // using the signal name declared by modport.
Index
Interface
Ports
Interface Methods
Clocking Block
Virtual Interface
Svtb N Verilog Dut

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