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TOP


Verilog Top



Top level module containts the design and testbench instance. Top module also contains clock generator. There is no need to instantiate the top module. Testbench and dut instances are connected using interface instance. Make an instance of env class and creat it. Call the do_test() method which starts the testbench components.



CODE: top.v
`include "mem_env.sv"

module top();


// Make an instance of SystemVerilog interface.
switch_if intf();



//As the RTL is in verilog and the SV Interface ports are not used,Connect signals by signal names
switch switch1 (.clk (intf.clock),
.reset (intf.reset),
.data_status (intf.data_status),
.data (intf.data_in),
.port0 (intf.data_out[0]),
.port1 (intf.data_out[1]),
.port2 (intf.data_out[2]),
.port3 (intf.data_out[3]),
.ready_0 (intf.ready[0]),
.ready_1 (intf.ready[1]),
.ready_2 (intf.ready[2]),
.ready_3 (intf.ready[3]),
.read_0 (intf.read[0]),
.read_1 (intf.read[1]),
.read_2 (intf.read[2]),
.read_3 (intf.read[3]),
.mem_en (intf.mem_en),
.mem_rd_wr (intf.mem_rd_wr),
.mem_add (intf.mem_add),
.mem_data (intf.mem_data));


// Creat a clock generator.
initial begin
intf.clock = 0;
#10;
forever begin
#5 intf.clock = !intf.clock;
end
end

// Make an instance of testbench env
sw_env env;

initial
begin
@(posedge intf.clock);
// Pass the interface to testbench environment.
env = new(intf);
//Call do_test task. extecution of the testbench starts.
env.do_test;
$finish;
end

endmodule //top

Index
Avm Introduction
Dut Specification
Rtl
Top
Interface
Environment
Packet
Packet Generator
Configuration
Driver
Reciever
Scoreboard

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