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AVM INTRODUCTION



Mentor Graphics Advanced Verification Methodology(AVM) is opensource and non-properietary SystemVerilog and systemc methodology. This is based on OSCI(open systemC initiative) TLM standared. AVM can be downloaded for free from mentors website. AVM contains TLM(Transaction Level modaling) concepts, rules, suggesation with lot of examples for better understanding. AVM focuses on constrained randomization, Coverage , Assertions & scorboarding.

AVM provides base classes to improve user productivity. AVM has TLM interfaces to communicate between testbench components. AVM liberary has the following base classes.

Reporting class: Has reporting methods, verbosity level controls etc.
Building Blocks: avm_transaction, avm_stimulus, avm_in_order_comparator, avm_env etc.
TML library: TLM inteaces, TLM channels.

Verification components can be class or modules. Modules are handy for HDL users. One of the main advantage of using module based avm testbench is it supports system verilog assertions.In SystemVerilog ,Assertions canot be part of class.

Where as class are more flexible as they are OO. Randomization is easy with class. Dynamic instancsation and classes can be used as varibles for communication.

AVM components intarect with DUT using SystemVerilog virtual interface.

Hear Im going to discussing the avm base classes which are used in the example. For more details refer to avm cookbook.


Tlm:



All the verification components use TLM interfacess whether they are class based or module based. Main operations on the TLM or put,get and peek.

Initiator puts transaction to a target and can get trasaction from a target.

There are two types of TLMs.
BLOCKING MODEL: Waits until the put transaction is completed befor the next put operation. Blocking operation is time consuming.
NON BLOCKING MODEL: Nonblocking operations are instansations. Every thing happens in zero time.

TLM supports unidirectional and bidirectional data flow. tlm_fifos are bases for TLM. tlm_fifo has put,peek(get a copy) and get interface for communication tranctions. It also has put_ap,get_ap(analaysis ports for commucating with score board or covarage model).

Lets see how to use ports and exports.
The TLM interface is called port. tlm_fifo sub blocks are called export.


EXAMPLE
Declare a tlm_fifo:

tlm_fifo#(packet) gen2drv;

Creat put port in initiator block(lets call it gen):
tlm_blocking_put_if#(packet) put_port;

Creat get port in target block(lets call it drvr):
tlm_blocking_get_if#(packet) get_port;

Connect the exports to ports:

gen.put_port = gen2drv.blocking_put_export;
drvr.get_port = gen2drv.blocking_get_export;

Noe put can be done in gen and get can be done in drvr.

Building Blocks





There are two types of bases class used for building AVM components.
1)avm_named_component
2)avm_verificatino_component.

avm_named_components has information about the hierarchy of the instantiatio and are used for TLM port and export connections. This also has built in message controlling system.

avm_verification_components are inherited from avm_named_component. avm_verification_component are used to build testbench component like driver,monitor,transactor etc. In addition to avm_named_component feauters, a run() method is provided for uses to define, and this run() method is forked from avm_env automatically.



Avm_transactors:



Avm transaction is base class for creating tranctions. In order to allow the avm and tlm libraries to work, we need methods to print, compare and clone transactions.

For any given transaction, T, to do four things to use avm_transaction:
Inherit from avm_transaction
Implement the virtual function string convert2string. This is for messaging.
Implement a function bit comp( input T t ). Used by the comparators for checking in scoreboard.
Implement a function T clone(). This used for tlm_fifos. clone() returns a copy() of .this(its object handle).




Avm_env:



avm_env class is the top level of testbench. avm_env has do_test() method which starts building and execution of the testbench components.

Environment execution stars when do_test() task is called.
There are 5 execution phases.
Construct: Constructs all the class based verification components.
Connect: Connect the class based verification components together.
Configure: Configuration of the testbench components in Zero time.
Execute: do_run() forks off all the components run() methods and then execute method.
Report: End of simulation messages goes hear.


Avm_messaging:



avm_messaging supports four types of severity levels. They are MESSAGE,WARNING,ERROR,FATAL
avm_messaging supports four types of actions. They are DISPLAY,LOG,COUNT,EXIT.
Each of the actions are define by severity and id.



Index
Avm Introduction
Dut Specification
Rtl
Top
Interface
Environment
Packet
Packet Generator
Configuration
Driver
Reciever
Scoreboard

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