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EVENT SIMULATION




The Problem of race condition exists if the SVA is sampling the signals exactly at specified event. So in SystemVerilog , the language has very clear semantics to avoid race condition while evaluating SVA.






In SV, a new region is added before Active region called preponed. So sampling for SVA is done in preponed region. No assignments are not done in preponed region. Signals are stable from previous timeslot and they are occurring before active and NBA ,so the race condition is avoided by this new preponed region. Look at the diagram, regions which are in light cyan color are for SVA.

IN preponed region only sampling is done , the evaluation of these sampled values are done in another region called observed region. Observed region occurs after NBA region. Even though the assignments are done in active ,inactive,NBA region, these updates are not used in observed region. Only signals sample in preponed region are used in observed region. Observed region occurs before reactive region where the testbench executes.

But in immediate assertions, the updated values in previous regions of current time slot are used in observed region.




Index
Introduction
Event Simulation
Assertion Types
Assertion System Tasks
Concurrent Assertion Layers
Sequences
Properties
Verification Directive

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