SystemVerilog adds features to specify assertions of a system. An assertion specifies a behavior of the system. Assertions are primarily used to validate the behavior of a design. In addition, assertions can be used to provide functional coverage and generate input stimulus for validation.
The evaluation of the assertions is guaranteed to be equivalent between simulation, which is event-based, and formal verification, which is cycle-based.
SystemVerilog allows assertions to communicate information to the test bench and allows the test bench to react to the status of assertions without requiring a separate application programming interface (API) of any kind
Advantages Of Assertion:
Reduces the debug time.
Bugs can be found earlier and are more isolated.
Controllable severity level.
Can interact with C functions.
Describe the Documentation and Specification of the design.
What Assertions Can Verify:
Assertions can be used to capture the information about various level of properties.
conceptual : can be used to verify systemlevel properties which are more architectural level.
design : These expresses unit level properties.
programming: More specified at RTL level.
1)conditional: It checks the some conditinal to be true using boolean expressions.
2)sequence : Checks whether the properties arr true using temporal expression.
3)signal : Checks on signal types.
a)x detection :Can be used to detect unconnected ports or undriven signal.
b)encoding types: Checks whether the encoding is violated.